SST-ERAS Tutorial

April 23rd, Sunday - 1:00 - 5:00 pm, Sheraton Raleigh Hotel, Downtown, Raleigh, NC
(Room: Governor I)
 
 

About the Tutorial

With a proliferation of custom IPs in the market, it is becoming increasingly challenging for Architects to integrate these IPs at system-level to evaluate their performance and drive design space exploration. Architects put in considerable effort and focus on low-level integration details to ensure its functional equivalence with performance model. To mitigate this problem, we propose our framework ERAS that provides a platform for swift integration of RTL IP models (convertible to C-description) with high-level architecture simulators such as Structural Simulation Toolkit (SST). The integration workflow automatically generates the SST wrapper component based on user description and carries necessary interfaces to 'plug' the RTL model with the SST framework.

Organizers

Clay Hughes (Sandia National Laboratories), Gwen Voskuilen (Sandia National Laboratories), Amro Awad (NC State University), Shubham Nema (NC State University), Shiva Kaushik Chunduru (NC State University)
 

Schedule

Content Presenters Affiliation Time
Part 1: Introduction to SST
Part 2: SST Overview
            SST Element Libraries: A tour
Clay Hughes, Gwen Voskuilen Sandia National Laboratories 1:00 PM - 2:30 PM
            Coffee Break - - 2:30 PM - 3:00 PM
Part 1: ERAS Overview
Part 2: Why ERAS ?
            Framwork Details
Shubham Nema NC State University 3:00 PM - 3:45 PM
           ERAS Demo Shiva Kaushik Chunduru NC State University 3:45 PM - 4:30 PM
          Questions ?
          Brainstorming		 Organizers SNL & NC State 4:30 PM - 5:00 PM

SST Simulator

                       
The Structural Simulation Toolkit (SST) was developed to explore innovations in highly concurrent systems where the ISA, microarchitecture, and memory interact with the programming model and communications system. The package provides two novel capabilities. The first is a fully modular design that enables extensive exploration of an individual system parameter without the need for intrusive changes to the simulator. The second is a parallel simulation environment based on MPI. This provides a high level of performance and the ability to look at large systems. The framework has been successfully used to model concepts ranging from processing in memory to conventional processors connected by conventional network interfaces and running MPI.

ERAS Framework

                       
The Structural Simulation Toolkit (SST) architectural simulator is being actively used to drive design space exploration of various architectural models and optimizations for hardware and software used by Architects.

The ability to augment the designs and architectural models explored in SST with low-level highly-accurate models, possibly with publicly available third-party IPs, can enable:
  1. fast evaluation of the performance impact for alternative IPs in designs of interest;
  2. enable system-level studies for using realistic IPs even before the technology or products are available;
  3. save significant efforts for modeling architectural components,typically integrated as-is, by just leveraging low-level models already available;
  4. facilitate more realistic design space exploration driven by real-world constraints of the used IPs (e.g., port width, interface protocol, interoperability, etc.);
  5. accurate performance evaluations of sub-systems of interest and understanding possible limitations of alternative IPs/implementations rather than using abstracted medium-fidelity designs.
Hence, we propose ERAS that systematically addresses these challenges and enables a versatile solution for seamless integration of low level designs into architectural simulators. Above figure depicts our vision for the future of architectural simulators and where ERAS framework fits in the architectural simulation workflow.

                       
The framework leverages the Essential Signal Simulation by Netlist Transforms(ESSENT) [1] tools to generate a C-model from a model described in FIRRTL, which is an Intermediate Representation (IR) for any Hardware Description Language (HDL). The hardware description can be written in Verilog or Chisel[2], which is a popular Hardware Construction language written in Scala [3], and can be converted to FIRRTL using the Chisel compiler. Similarly, hardware descriptions written in Verilog can be lowered to FIRRTL using Yosys [4]. The generated C-model is fed to the parser, the core of the ERAS, that generates architectural components integrable with SST.  

ERAS Contributors

 
Principal Investigator
Collaborators (Sandia National Laboratories)
Developers

Tutorial Resources


ERAS Slides:
   

 Technical Report: ERAS  

 Tutorial Exercises:

  • demo.py Running an example SST simulation (01_Overview, slide 25 "Running a simulation")
  • exercise.py Base script for the exercises in 02_Configuring. Same as the demo script.
  • solutions/ Solutions for exercies 1-4 in the 02_Configuring slides
 Slides & Exercise Link: https://github.com/sstsimulator/sst-tutorials/tree/master/ispass2023  

References

  1.   Beamer, Scott, and USDOE. Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) v1.0. Computer software. https://www.osti.gov//servlets/purl/1572345. USDOE. 3 Jul. 2019. Web. doi:10.11578/dc.20191029.3
  2.   Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, and Krste Asanović. 2012. Chisel: constructing hardware in a Scala embedded language. In Proceedings of the 49th Annual Design Automation Conference (DAC '12). Association for Computing Machinery, New York, NY, USA, 1216–1225. https://doi.org/10.1145/2228360.2228584
  3.   Odersky, Martin, Philippe Altherr, Vincent Cremet, Burak Emir, Stphane Micheloud, Nikolay Mihaylov, Michel Schinz, Erik Stenman, and Matthias Zenger. "The Scala language specification." (2004).
  4.   Wolf, Clifford, Johann Glaser and Johannes Kepler. “Yosys-A Free Verilog Synthesis Suite.” (2013).